1. Field Of The Invention
This invention relates to semiconductor devices and, more particularly, to the use of a polysilicon layer for local interconnect in a CMOS technology incorporating silicon dioxide sidewall spacers.
2. Description Of The Relevant Art
The use of a polysilicon layer for local interconnect has been reported in the literature for both bipolar and MOS technologies. In bipolar processes, a polysilicon layer can be used to electrically contact the base and collector regions of bipolar transistors. In MOS technologies, a polysilicon layer can be used to electrically contact the source-drain regions of the MOS transistors. The electrical contacts so formed are termed "buried contacts." By suitable patterning of the polysilicon layer forming the buried contacts, a local interconnect may be formed. Global interconnects then are formed by contacting the polysilicon layer using conventional metal interconnects.
In the past, local interconnects were formed using metal interconnects. Since the number of metal layers which may be formed on a given portion of a wafer is limited, the use of a polysilicon layer for local interconnect allows the metal layer that was formerly used for local interconnect to be employed as an additional global interconnect layer. In addition to the advantages in layout provided by an additional global interconnect layer, the use of a polysilicon layer to form device contacts also results in an improvement in transistor performance through reduction in device parasitic areas (e.g., the extrinsic base area in bipolar transistors) It also results in simplification of contact etch technology for shallow junctions where very high etch selectivity to the substrate is required. This is particularly important in processes where dielectric planarization is performed before contact etch, because the thickness nonuniformity of the dielectric creates a substantial risk of etching into the shallow junction. By using a polysilicon layer to contact the shallow junction, metal contacts may be made to the polysilicon layer rather than the shallow junction, and the risk of overetching is eliminated.
Known devices which use a polysilicon layer for local interconnect do not employ silicon dioxide sidewall spacers on the polysilicon layer. For example, FIG. 1 shows a semiconductor structure 1 wherein a polysilicon layer 2 forms a buried contact 3 to an active region 5. Structure 1 is silicided so that a silicide layer 6 extends over the top and sides of polysilicon layer 2 and thereafter along the surface of active region 5. Consequently, a source or drain current I.sub.S/D flows primarily along the silicided surface 6 to the active region 5.
In advanced CMOS or BiCMOS processes having very high packing densities, oxide sidewall spacers 7 (FIG. 2) are essential to ensure electrical isolation between polysilicon layer 2 and the polysilicon layer forming the gate (not shown). However, any silicide layer 6 now formed is discontinuous because no silicide forms over the oxide sidewall spacers 7. Consequently, a source/drain current I.sub.S/D flowing along the silicide layer 6 on the upper surface of polysilicon layer 2 must flow through the buried contact 3 and into the active region 5, beneath the sidewall spacer 7, and thereafter back to the silicided portion 6 of the active region 5. Because current must cross the buried contact 3 between the polysilicon layer 2 and the active region 5, a high series resistance may result. This high series resistance can degrade the performance of the device below acceptable levels in many applications. As a natural result of this concern, the use of a polysilicon layer for local interconnect in the presence of sidewall spacers has been avoided.
Finally, known devices which use a polysilicon layer for local interconnect limit contacts to N-type active regions to avoid the additional steps required when processing a polysilicon layer with differently doped regions. This hinders the flexibility of the polysilicon interconnect scheme or eliminates it altogether.